This invention relates to a designing method aiming power integrity of a semiconductor chip included in the semiconductor package and to a design aid system and a computer program product in both of which the method is implemented. The invention also relates to a semiconductor package manufactured in accordance with the method.
In a semiconductor chip such as a dynamic random access memory (DRAM) chip, transient currents flow at a power supply pad and a ground pad of the semiconductor chip, for example, when an output driver of the semiconductor chip changes its output state, i.e. from high level to low level, or from low level to high level. The transient currents cause voltage fluctuations at the power supply pad and the ground pad.
If the above-mentioned voltage fluctuations exceed a certain level, the semiconductor chip fails to function properly. Therefore, each semiconductor package including the semiconductor chip should be designed in consideration of a suitable voltage fluctuation limitation. Namely, each semiconductor package should be designed so that the voltage fluctuations at the power supply pad and at the ground pad of the semiconductor chip do not exceed the voltage fluctuation limitation.
Regarding the above, one of conventional approaches is based on a transient analysis using a SPICE (Simulation Program with Integrated Circuit Emphasis) model. Such a transient analysis is disclosed in JP-A 2004-54522. According to the conventional transient analysis, a user can judge whether a designed semiconductor package violates the voltage fluctuation limitation therefor.
However, according to the conventional transient analysis, nobody can identify a problematic section of each semiconductor package. Therefore, even if a violation is found as a result of the transient analysis, a design of the semiconductor package is modified without information about the problematic section. Hence, such design modification is normally carried out multiple times by trial and error, in accordance with the conventional transient analysis, so that its design cycle needs long time. The same goes for a semiconductor apparatus including a semiconductor package as mentioned above.